Intel will ship computers with an experimental 48-core processor to researchers by the end of the second quarter as the company tries to reshape its future chips.
Limited quantities of the processor will be sent primarily to academic institutions, said Sean Koehl, technology evangelist with Intel Labs, during an event in New York on Wednesday. The chip may not become commercially available as it is part of a research project, but features from the processor could be implemented in future chips.
Development of the processor is part of Intel’s terascale computing research program. A focus area of the program is to put more cores in a single processor to enable faster computing in devices ranging from mobiles to servers.
The 48-core chip operates at about the clock speed of Atom-based chips, said Christopher Anderson, an engineer with Intel Labs. Intel’s latest Atom chips are power-efficient, are targeted at netbooks and small desktops, and run at clock speeds between 1.66GHz and 1.83GHz. The 48-core processor, built on a mesh architecture, could lead to a massive performance boost when all the chips communicate with each other, Anderson said.
Adding cores to processors is considered a power-efficient way of boosting chip performance. The traditional way of boosting performance was by cranking up CPU clock speed, but that led to excessive heat dissipation and power consumption.
Intel and its rival Advanced Micro Devices last week announced new server chips with their highest core counts to date. Intel announced Xeon 7500 and 6500 processors for high-end servers, which included eight-core chips, while AMD announced Opteron 6100 chips with 12 cores.
The 48-core processor’s architecture includes improvements that cut memory and communication bottlenecks that affect current x86 chips. For faster data exchange, the chip topology organizes the cores with multiple points to receive and transfer data. Routers between cores facilitate faster data exchange and the architecture is expandable as cores are added. The 48-core chip has 24 small routers between cores, Koehl said.
Each core has on-chip buffers that can instantly exchange data in parallel across all the cores, Koehl said.